In an era dominated by IoT applications, sensors are everywhere—embedded in our homes, vehicles, industries, and even our bodies. They generate an immense amount of data that holds valuable insights waiting to be uncovered. Traditional DSP algorithms like the Fast Fourier Transform (FFT) and Kalman filters have been fundamental in analysing this data, effectively extracting features of interest and filtering out noise. These algorithms excel in tasks such as frequency analysis, state estimation, and noise reduction, providing precise and reliable results.
However, as the complexity and volume of sensor data grow, relying solely on DSP algorithms is no longer sufficient. The patterns and anomalies within large-scale, multidimensional data streams often exceed the capabilities of traditional methods. This is where AI and ML models become indispensable. AI/ML models are adept at handling complex, nonlinear patterns and can make predictions based on learned data. Yet, they lack common sense of the process that they are modelling and are also highly dependent on the quality of the input data.
Combining the strengths of both DSP algorithms and AI/ML models leads to more robust and efficient sensor data processing systems. DSP techniques can preprocess and enhance the data, making it cleaner and more relevant for AI models to analyse. Arm Cortex processors play a pivotal role in this augmentation. Renowned for their efficiency and performance, they are widely used in AIoT (Artificial Intelligence of Things) solutions, enabling the simultaneous execution of DSP algorithms and AI/ML models directly on edge devices. This combination allows for intelligent data processing that is both rapid and power-efficient, meeting the demands of modern technology applications.
The Necessity of DSP Algorithms
DSP algorithms are essential for transforming raw sensor data into meaningful information. Sensors often collect data that is noisy or distorted, making direct interpretation challenging. DSP algorithms tackle these issues by performing noise reduction, signal enhancement, and feature extraction.
For example, the FFT converts time-domain signals into frequency-domain representations, revealing patterns crucial for applications like vibration analysis and audio. Digital filters such as lowpass, bandpass and high-pass eliminate unwanted frequency regions, isolating signals of interest and improving data quality.
Without DSP techniques, valuable insights within sensor data might remain hidden. DSP algorithms lay the groundwork by refining the data, ensuring that both traditional analysis methods and AI/ML models receive high-quality inputs. They provide reliable results based on established mathematical principles and human reasoning, which is essential in critical applications like medical devices, aerospace, and industrial automation where precision and repeatability are paramount.
As such, it’s important to realise that preprocessing of sensor data with DSP algorithms is an essential step, since AI/ML models rely heavily on the quality of input data for accurate predictions.
Moreover, DSP algorithms are efficient and can operate in real-time on devices with limited resources, such as Arm Cortex processors, making them ideal for edge computing where real-time processing is needed.
State-of-the art AIoT microcontrollers
The Arm Cortex-M52, M55 and M85 are targeted for AIoT applications on microcontrollers. These processors use Arm’s powerful Armv8.1-M architecture that implement their M-Profile Vector Extension (MVE) technology (nicknamed Helium) allowing for 128bit vector mathematical operations (such as dot product operations) needed for ML and some DSP algorithms.
However, as only a few IC vendors (Alif, Ambiq, Samsung, Renesas, HiMax, Bestechnic, Qualcomm) have currently released or are planning to release any devices, Helium processors remain a gem for the near distant future.
The Necessity of AI/ML Models
While DSP algorithms are powerful, they are generally designed to address specific problems and may not scale well with the increasing complexity and volume of sensor data. AI/ML models come into play by offering the ability to learn from data, identify complex patterns, and make predictions without explicit programming for each task. They are particularly useful when:
Patterns are too complex for manual feature extraction: In cases like image and speech recognition, where the features of interest are not easily extracted using traditional DSP methods.
Data is high-dimensional or unstructured: AI/ML models can handle large datasets with numerous variables, finding relationships that may not be apparent using scientific reasoning.
Adaptive learning is required: ML models can be improved over time with more training data as it becomes available.
However, it is important to realise that AI/ML models lack common sense and are heavily reliant on the data they are trained on. As such, they may misinterpret or overlook important features if the input data is noisy or lacks proper pre-processing.
Augmenting DSP and AI/ML: a complementary approach
To maximize the benefits of sensor data processing, a hybrid approach that combines DSP algorithms with AI/ML models is often the most effective. Here’s how they complement each other:
Pre-processing with DSP:
Noise Reduction: Digital filters (e.g. lowpass) can be used to clean up the signal before it reaches the ML model.
Feature Extraction: Algorithms like FFT or DWT can extract meaningful features that reduce the dimensionality of the data and highlight important patterns.
AI/ML for Pattern Recognition:
Classification and Regression: ML models can take the features extracted by DSP algorithms and perform tasks like anomaly detection, predictive maintenance, and classification.
Adaptive Learning: ML models can adapt to new data trends over time, improving their accuracy and usefulness.
Feedback Mechanisms:
Model Refinement: The outputs from AI/ML models can inform adjustments in DSP algorithms, creating a feedback loop that enhances overall system performance.
Example Application: Vibration analysis in Industrial equipment
DSP Stage:
FFT Analysis: Converts vibration signals (usually captured from an accelerometer) from the time to frequency domain to identify characteristic frequencies associated with specific mechanical faults.
Feature Extraction: Extracts features like peak frequencies, amplitudes, and harmonics. These amplitude features can be further scaled (using properties of the FFT) to extract velocity or displacement estimates from the original acceleration data.
AI/ML Stage:
Fault Classification: An ML model trained on labelled data predicts the type of fault (e.g., imbalance, misalignment, bearing wear) based on the extracted features.
Predictive Maintenance Scheduling: Regression models estimate the remaining useful life of equipment, allowing for proactive maintenance.
Benefits of augmentation:
Improved Accuracy: Pre-processing with DSP algorithms enhances the quality of data fed into AI/ML models.
Efficiency: Reduces computational load by focusing on relevant features, which is especially important for edge devices with limited resources.
Reliability: Combining deterministic DSP outputs with probabilistic AI/ML predictions leads to more robust systems.
Detecting motor faults via harmonic fingerprint analysis
Key takeaways
The fusion of DSP algorithms and AI/ML models represents a powerful paradigm for sensor data processing in modern technology. DSP algorithms provide the necessary tools for signal enhancement and feature extraction, ensuring that the data is in the best possible form for analysis. Despite lacking any common sense (see here for a previous article), AI/ML models certainly excel at finding complex patterns and making predictions based on the processed data, making them attractive for many modern AIoT applications.
Arm Cortex processors play a pivotal role in this integration, offering the computational capabilities required to run both DSP algorithms and AI/ML models efficiently on the same platform. This synergy enables the development of advanced AIoT solutions that are capable of processing sensor data intelligently at the edge, leading to faster decisions and reduced latency. This is further strengthend with Arm’s TrustZone extension, that provides developers with a hardware data security model, offering a high level of security against hacking, stealing of encryption keys and counterfeiting.
As the volume and complexity of sensor data continue to grow, leveraging the strengths of both DSP and AI/ML will be essential for advancing technology across industries. By adopting a complementary approach and utilising decent computational platforms such as Arm’s Cortex family of processors, we can build more effective, efficient, and intelligent systems that meet the demands of the future.
Sanjeev is an AIoT visionary and expert in signals and systems with a track record of successfully developing over 25 commercial products. He is a Distinguished Arm Ambassador and advises top international blue chip companies on their AIoT solutions and strategies for I4.0, telemedicine, smart healthcare, smart grids and smart buildings.
https://www.advsolned.com/wp-content/uploads/2024/11/futuristic_sensors-scaled-e1732806588596.jpg4411029Dr. Sanjeev Sarpalhttps://www.advsolned.com/wp-content/uploads/2018/02/ASN_logo.jpgDr. Sanjeev Sarpal2024-11-28 16:03:252024-12-02 13:57:40Maximizing IoT sensor performance: Getting the most out of your sensor with DSP and AI
In the rapidly evolving landscape of digital transformation, organizations are increasingly leveraging Real-Time Edge Intelligence (RTEI) solutions to enhance operational efficiency and decision-making capabilities. RTEI refers to the deployment of advanced data processing and analytics at the edge of the network (i.e. closer to where data is generated) rather than relying solely on centralized cloud infrastructure. This approach successfully addresses the challenges posed by traditional data processing methods and offers significant benefits across multiple sectors, particularly when building solutions with Arm processor technology.
Key concepts of Real-Time Edge Intelligence
Improved Response Times: RTEI enables immediate data processing and analysis, resulting in faster decision-making. For industries like healthcare, manufacturing, and transportation, this can mean the difference between success and failure in critical situations. Arm processors allow for high-performance computing in compact form factors, making them ideal for real-time applications.
DSP/ML at the Edge: Arm’s extensive ecosystem of partner solutions and in-built algorithmic accelerator technology makes deploying DSP algorithms and ML models on the edge very easy. This enables RTEI solutions to provide real-time insights and predictions of the process that they’re monitoring, empowering organizations to automate processes and respond dynamically to changing conditions.
Data cleaning and feature extraction: Arm-based devices can clean noisy sensor data and extract features interest at the edge, sending only relevant data to the cloud. This minimizes bandwidth usage and optimizes network performance, ensuring that only critical data is transmitted. Arm’s low-power architecture is ideal for this task, allowing devices to perform complex computations in battery-powered applications.
Cost Efficiency: By reducing the amount of data sent to the cloud, organizations can lower bandwidth costs and cloud storage expenses. The efficient processing capabilities of Arm processors allow for more effective resource use, leading to operational cost savings. Their energy efficiency further contributes to reduced operational costs in large-scale deployments.
Increased Reliability: RTEI solutions can operate independently of cloud connectivity, ensuring that essential mission-critical applications continue to function even during a network outage. The robustness of Arm technology in various environmental conditions enhances system reliability and operational resilience, particularly in remote locations, typically encountered in many IoT applications.
Scalability: Arm-based solutions can be easily scaled to accommodate growing data volumes and an increasing number of connected devices. The modularity of Arm architecture supports the development of a diverse ecosystem of devices, making it easier for organizations to adapt to changing business needs.
Enhanced security and privacy with Arm TrustZone
Security is a critical concern for edge devices, particularly those handling sensitive data. Arm TrustZone (Cortex-M33, Cortex-M52 and Cortex-A) implements a security paradigm that discriminates between the running and access of untrusted applications running in a Rich Execution Environment (REE) and trusted applications (TAs) running in a secure Trusted Execution Environment (TEE). The basic idea behind a TEE is that all TAs and associated data are secure as they are completely isolated from the REE and its applications. As such, this security model provides a high level of security against hacking, stealing of encryption keys, and counterfeiting, and as such provides an elegant way of protecting sensitive client information.
DSP support for Algorithms
DSP is critical for many RTEI applications, including audio and video processing, sensor signal processing and data analysis. Arm’s broad range of processors offer extensive DSP capabilities, allowing for the implementation of complex algorithms in floating-point. The Cortex-M family dominates the low-power micro-controller market as described below, whereas the more powerful Application or Cortex-A processors target mini-computers, such as the Raspberry Pi and smartphones etc. The Cortex-R family targets real-time safety-critical applications, such as automotive and radar.
All three types of processors offer algorithmic support, but the Cortex-M family is particularly interesting, as it adds DSP functionality to low-power microcontroller devices making it highly desirable for the IoT market, as we now discuss in the following section.
Cortex-M processors
Although a few processor technologies exist for microcontrollers (e.g. RISC-V, Xtensa, MIPS), over 90% of the microcontrollers used in the smart product market are powered by so-called Arm Cortex-M processors that offer a combination of high algorithmic performance, low-power and security. The Arm Cortex-M4 is a very popular choice with several silicon vendors (including ST, TI, NXP, ADI, Nordic, Microchip, Renesas), as it offers DSP (digital signal processing) functionality traditionally found in more expensive devices and is low-power.
Acceleration of DSP calculations
The Armv7E-M architecture supports a DSP extension that implements an SIMD (single instruction, multiple data) architecture extension that can significantly improve the performance of an algorithm. The basic idea behind SIMD involves parallel execution of an instruction (e.g. Add, Subtract, Multiply, Divide, Abs etc) on multiple data elements via the use of 64 or 128-bit registers. These DSP extension intrinsics (SIMD optimised instruction) support a variety of data types, such as integers, floating and fixed-point.
The high efficiency of the Arm compiler allows for the automatic dissemination of your C code in order to break it up into SIMD intrinsics, so explicit definition of any DSP extension intrinsics in your code is usually unnecessary. The net result for your application is much faster code, leading to better power consumption and for wearables, better battery life.
What algorithmic operations would use this?
The following examples give an idea of operations that can be significantly speeded up with SIMD intrinsics:
vadd can be used to expedite the calculation of a dataset’s mean. Typical applications include average temperature/humidity readings over a week, or even removing the DC offset from a dataset.
vsub can be used to expedite numerical differentiation in peak finding for a sinewave tracking application.
vabs can be used for expediting the calculation of an envelope of a fullwave rectified signal in EMG biomedical and smartgrid applications.
vmul can be used for windowing a frame of data prior to FFT analysis. This is also useful in audio applications using the overlap-and-add method.
The hardware floating point unit is very good for expediting MAC (multiply and accumulate) operations used in digital filtering, requiring just three cycles to complete. Other DSP operations such as add, subtract, multiply and divide require just one cycle to complete.
Key takeaways
As organizations continue to embrace digital transformation, Real-Time Edge Intelligence (RTEI) solutions, particularly when integrated with Arm processor technology, stand out as key enablers of innovation and efficiency. By harnessing the power of edge computing and the performance advantages of Arm’s Cortex-A and Cortex-M architectures, the security benefits of Arm TrustZone, and the DSP capabilities for advanced algorithms, businesses can achieve rapid decision-making, enhance security, and optimize operational costs. The future of data processing lies at the edge, and those who adopt RTEI solutions powered by Arm technology will be well-positioned to thrive in an increasingly competitive landscape.
Sanjeev is an AIoT visionary and expert in signals and systems with a track record of successfully developing over 25 commercial products. He is a Distinguished Arm Ambassador and advises top international blue chip companies on their AIoT solutions and strategies for I4.0, telemedicine, smart healthcare, smart grids and smart buildings.
Unexpected equipment failures can be expensive and potentially catastrophic, resulting in unplanned production downtime, costly replacement of parts and safety and environmental concerns. With many factories and process control plants facing an ever-increasing shortage of experienced personnel, many are now looking for AI based systems to replace the ‘experienced old guy’ who knows everything about the machine and reduce their Total Cost of Ownership (TOC).
The challenge is however, how do you build and train an AI CbM system to replace an expert ?
What is CbM?
As part of the I4.0 revolution, Condition based monitoring (CbM) of machines has received a great amount of attention, as factories look to maximise their production efficiency and reduce their TOC, while at the same time retaining the invaluable skills of experienced foremen and production workers. As such, CbM is a process for monitoring equipment during operation to identify any deterioration, enabling maintenance to be planned and operational costs reduced.
CbM 5G edge computing
Many are factory owners are suspicious of cloud-based enterprise solutions offered by Microsoft, Amazon and Google as data leaves the site and any latency issues could affect production output. Recently 5G edge computing has received much attention, whereby all time-critical operations are undertaken at the edge (i.e. near to the asset in the factory) via smart sensors.
Arm’s rich set of Cortex processors offer a combination of high performance, ML/DSP computation support and low power. This is further strengthened by Arm’s new Helium Cortex-M55 and Cortex-M85 AI based processors that have been specially designed for edge-based AI applications – the latter offers an impressive 3DMIPS/MHz making it a good fit for ML and DSP algorithms. These processors and supporting libraries now allow developers to develop high-performance CbM smart sensors to perform their computationally intensive tasks at the edge and communicate the results via a 5G network to a smartphone or database. This provides higher reliability and scalability than expensive cloud-based solutions reliant on big data.
It would seem that big data has had its day!
Vibration sensor technology
Contactless MEMS (microelectromechanical systems) accelerometers sensors are an excellent alternative to the well-established, but bulky and expensive (25-500+ EUR) Piezo sensors for obtaining vibration information. MEMS sensors are relatively low cost (10-30 EUR) and can offer a response down to DC (zero Hertz), which is useful for the detection of imbalance at very low rotational speeds. MEMS accelerometers also have a self-test feature whereby the sensor can be verified to be 100% functional. They produce acceleration data that can be analysed by various vibration monitoring algorithms.
Spectral vibration monitoring via the FFT (Fast Fourier Transform) is regarded as an industry standard for machine vibration analysis. If a mechanical problem exists, the FFT spectra (multiple spectrums) will provide information to help determine the source and cause of the problem. Coupled with the right AI algorithms, the features from the FFT analysis can be used to identify the root cause of the failure, such as motor imbalance, misalignment, and looseness. These properties and challenges faced by the FFT will be discussed further later on in the article.
There are several steps to follow as guidelines to help achieve a successful vibration monitoring programme. The following is a general list of these steps:
Collect useful information: Look, listen and feel the machinery to check for resonance. Identify what measurements are needed (point and point type). Conduct additional testing if further data are required.
Analyse spectral data: Evaluate the overall values and specific frequencies corresponding to machinery anomalies. Compare overall values in different directions and current measurements with historical data.
Multi-parameter monitoring: Use additional techniques to conclude the fault type. (Analysis tools such as phase measurements, current analysis, acceleration enveloping, oil analysis and thermography can also be used.)
Perform Root Cause Analysis (RCA): In order to identify the real causes of the problem and to prevent it from occurring again.
Reporting and planning actions: Use a Computer Maintenance Management System (CMMS) to rectify the problem and take action to achieve a plan.
As aforementioned, a popular device used to obtain acceleration data is a so-called ‘accelerometer’. These devices are semiconductor-based MEMS (microelectromechanical systems) and provide 3D (i.e. tri-axial) acceleration time domain data to a supporting microcontroller.
Before FFT analysis, the accelerometer data is usually passed through integration signal processing blocks, in order to convert the time domain acceleration data into velocity and displacement data. These blocks are comprised of a highpass filter and cumulative sum (integration). The highpass filter is essential for removing the effects of DC and noise, which would cause an offset in the output (i.e. the result of the integration). Depending on the severity of the noise/DC the output may even saturate, making it unusable for analysis. The design of a suitable highpass filter is an extremely challenging task and is the primary reason why many vibration analysis systems struggle to measure vibrations <10Hz (600 RPM).
Collect useful information
When conducting a vibration program, certain preliminary information is needed in order to conduct an analysis. The identification of components, running speed, operating environment and types of measurements should be determined initially to assess the overall system.
Identify components of the machine that could cause vibration
Before a spectrum can be analysed, the components that cause vibration within the machine must be identified. For example, you should be familiar with these key components:
If the machine is connected to a fan or pump, it is important to know the number of fan blades or impellers.
If bearings are present, know the bearing identification number or its designation.
If the machine contains, or is coupled, to a gearbox, know the number of teeth and shaft speeds.
If the machine is driven with belts, know the belt lengths.
The above information helps assess spectral components and helps identify the vibration source. Determining the running speed is the initial task. There are several methods to help identify this parameter.
Identifying the running speed
Knowing the machine’s running speed is critical when analysing an FFT spectrum. Running speed is related to most components within the machine and therefore, aids in assessing overall machine health. There are several ways to determine running speed:
Read the speed from instrumentation at the machine or from instrumentation in the control room monitoring the machine.
Look for peaks in the spectrum at 1,800 or 3,600 RPM (60Hz countries), 1,500 and 3,000 RPM (50Hz countries) if the machine is an induction electric motor, as electric motors usually run at these speeds. If the machine is variable speed, look for peaks in the spectrum that are close to the running speed of the machine during the time at which the data is captured.
An FFT’s running speed peak is typically the first significant peak in the spectrum when reading the spectrum from left to right. Search for this peak and check for peaks at two times, three times, four times, etc. (at the harmonic frequencies).
Challenges with the FFT algorithm
FFT spectra allow us to analyse vibration amplitudes at various component frequencies on the FFT spectrum. In this way, we can identify and track vibration occurring at specific frequencies. Since we know that particular machinery problems generate vibration at specific frequencies, we can use this information to diagnose the cause of excessive vibration.
Challenges with spectral analysis
The sampling rate of the accelerometer drifts with temperature: This results in a mismatch between the FFT analysis sampling frequency and the real situation. As such, the amplitude and frequency estimates of the vibration will be incorrect.
Frequency resolution: the frequency of the vibration peak may have a fractional value. If the resolution of the Fourier algorithm is not fine enough, it will ‘smear’ the result, resulting in a lower amplitude estimate.
Running speed: this is typically known apriori, but will have a degree of error associated with it and will change with temperature. For example, 3000 rpm ±1% is 50Hz ±0.5Hz at the fundamental running frequency. In order to track higher harmonics (i.e. multiples of the running speed) the FFT must have sufficient frequency resolution to accurately estimate the amplitude at the right frequency.
Traditional FFT based analysis uses a very high number of computational points in order to achieve a 1Hz resolution. Although this is OK, it still does not overcome the fractional frequency components and requires considerable computational effort.
Some designs use a phaselocked loop, that tracks the running frequency and sets the FFT analysis sampling frequency to a multiple (e.g. 20x) of the running speed. Although this is a very good workaround, it requires specialised hardware (such as an expensive ASIC) and is inflexible for changes in running speed.
ML feature extraction, DSP algorithms and models
In order to build an ML (machine learning) model for an AI CbM application, several challenges need to be overcome.
Definition of classes: In order to make a classification, ML classes must be defined. In the simplest sense, this can be Fault or Normal behaviour, but what about other cases?
ML Features: what data features will be used for the ML model? Running speed, harmonics, RMS amplitude? What physical and mathematical principles should I use to build these algorithms?
Obtaining ML training data: How will you obtain suitable datasets for ML training? In many cases this is not easy to obtain, as many foremen will not allow any disruption to their time-critical production lines.
Preparing datasets: After answering the aforementioned questions, the next challenge will be to capture and prepare the datasets for the ML classification. This is traditionally where a good 90% of a data scientist’s time will be spent. Therefore, it is prudent to invest in high fidelity feature extraction edge algorithms in order to expedite this step. This will also have the advantage of increasing the reproducibility and consistency of the results, which is where many AI based systems perform poorly.
ASN’s IP blocks and applications
ASN’s vibration IP blocks combine the Fourier transform’s time-frequency integration property, data filtering and a specialised high frequency resolution tracking algorithm to implement the ARAHTA (adaptive running speed and harmonics tracking) algorithm. ARAHTA tracks the vibration sensor’s ODR (output data rate) and calculates the motor/pumps running speed using the sensor’s accelerometer sensor data in real-time. ARAHTA’s high resolution and adaptive tracking mechanism results in a typical running speed accuracy of ±1 RPM across the temperature range and sub-mm displacement accuracy using noisy accelerometer data.
ARAHTA’s high accuracy and flexibility ensures that the resulting ML features are high quality and very consistent in the presence of temperature change and load shifts. This has a significant advantage for CbM applications, whereby fingerprinting a spectral profile can be used to assess the degradation of assets of interest. ARAHTA’s high-resolution spectrum forms the basis of providing an AI algorithm with high accuracy feature-rich information, suitable for classification.
Algorithmic performance
A comparison of the FFT vs the ASN ARAHTA IP blocks is shown below. Setting up a test accelerometer signal comprised of an 8.2Hz sinusoid with amplitude 1gand a few harmonic frequencies at various amplitudes, we can objectively compare the methods.
Analysing Figure 1, notice that the plot shows a comparison of the acceleration spectrum (i.e. the FFT of the acceleration data, shown in red) and the displacement spectrum, shown in blue. Analysing the first peak, notice that as the FFT’s resolution is insufficient, as the algorithm has identified the peak at 8.75Hz, rather than at 8.2Hz. This has a consequence for the amplitude estimation, as the acceleration spectrum amplitude is around 0.34g, rather than the expected 1g. As such, the algorithm incorrectly estimates the displacement at 8.2Hz to be 1mm, rather than 3.69mm.
The true value can be seen in Figure 2, where ARAHTA correctly finds the first resonant peak at 8.2Hz and estimates the correct amplitude of 3.69mm.
Figure 1 – Displacement estimate via FFT (frequency resolution: 813.5mHz): wrong frequency and amplitude estimation
Figure 2 – Displacement estimate via ARAHTA (frequency resolution: 10mHz): correct amplitude and frequency estimation.
Get in touch and reduce your asset’s TCO
ASN contactless measurement sensor technology and smart algorithms are an ideal solution for AI based CbM applications. Please contact our CbM expert team to see how we can help you create an effective maintenance programme and reduce your asset’s Total Cost of Ownership.
Sanjeev is an AIoT visionary and expert in signals and systems with a track record of successfully developing over 25 commercial products. He is a Distinguished Arm Ambassador and advises top international blue chip companies on their AIoT solutions and strategies for I4.0, telemedicine, smart healthcare, smart grids and smart buildings.
https://www.advsolned.com/wp-content/uploads/2019/12/induction-motor-1500-580-4_compres2.jpg5801500Dr. Sanjeev Sarpalhttps://www.advsolned.com/wp-content/uploads/2018/02/ASN_logo.jpgDr. Sanjeev Sarpal2022-03-02 17:47:312023-05-12 09:23:54Deploying AI based CbM applications: challenges and algorithmic solutions
Filter mit unendlicher Impulsantwort (IIR) sind für eine Vielzahl von Sensormessanwendungen nützlich, einschließlich der Entfernung von Messrauschen und der Unterdrückung unerwünschter Komponenten, wie z. B. Stromleitungsstörungen. Obwohl mehrere praktische Implementierungen für den IIR existieren, bietet die Struktur Direct form II Transposed die beste numerische Genauigkeit für die Fließkomma-Implementierung. Wenn jedoch eine Festkomma-Implementierung auf einem Mikrocontroller in Betracht gezogen wird, gilt die Struktur Direkte Form I aufgrund ihres großen Akkumulators, der eventuelle Zwischenüberläufe aufnimmt, als die beste Wahl. Diese Application Note befasst sich speziell mit dem Entwurf und der Implementierung von IIR-Biquad-Filtern auf einem Cortex-M-basierten Mikrocontroller mit dem ASN Filter Designer sowohl für Fließkomma- als auch für Festkomma-Anwendungen über das Arm CMSIS-DSP Software-Framework.
Es werden auch Details (einschließlich eines Referenzbeispielprojekts) zur Implementierung des IIR-Filters in Arm/Keils MDK-Industriestandard-Cortex-M-Mikrocontroller-Entwicklungskit gegeben.
Einführung
ASN Filter Designer bietet Ingenieuren eine leistungsfähige DSP-Experimentierplattform, die den Entwurf, das Experimentieren und den Einsatz komplexer IIR- und FIR (Finite Impulse Response)-Digitalfilterdesigns für eine Vielzahl von Sensormessanwendungen ermöglicht. Die fortschrittliche Funktionalität des Tools umfasst einen grafikbasierten Echtzeit-Filterdesigner, mehrere Filterblöcke, verschiedene mathematische I/O-Blöcke, symbolisches Live-Mathe-Scripting und Echtzeit-Signalanalyse (über einen integrierten Signalanalysator). Diese Vorteile in Verbindung mit der automatischen Dokumentation und Code-Generierungsfunktionalität ermöglichen es Ingenieuren, ein digitales Filter innerhalb von Minuten statt Stunden zu entwerfen und zu validieren.
Das Arm CMSIS-DSP (Cortex Microcontroller Software Interface Standard) Software-Framework ist eine reichhaltige Sammlung von über sechzig DSP-Funktionen (einschließlich verschiedener mathematischer Funktionen wie Sinus und Kosinus; IIR/FIR-Filterfunktionen, komplexe mathematische Funktionen und Datentypen), die von Arm entwickelt und für die Cortex-M-Prozessorkerne optimiert wurden.
Das Framework macht ausgiebig Gebrauch von hoch optimierten SIMD-Befehlen (Single Instruction, Multiple Data), die mehrere identische Operationen in einem einzigen Befehlszyklus ausführen. Die SIMD-Befehle (sofern vom Core unterstützt) in Verbindung mit anderen Optimierungen ermöglichen es Ingenieuren, schnell und einfach hochoptimierte Signalverarbeitungsanwendungen für Cortex-M-basierte Mikrocontroller zu erstellen.
Der ASN Filter Designer unterstützt das CMSIS-DSP Software-Framework vollständig, indem er über seine Code-Generierungs-Engine automatisch optimierten C-Code auf Basis der DSP-Funktionen des Frameworks erzeugt.
Entwurf von IIR-Filtern mit dem ASN Filter Designer
Der ASN Filter Designer bietet Ingenieuren eine einfach zu bedienende, intuitive grafische Design-Entwicklungsplattform für den Entwurf von digitalen IIR- und FIR-Filtern. Das Echtzeit-Entwurfsparadigma des Tools nutzt grafische Entwurfsmarker, die es dem Designer ermöglichen, seine Anforderungen an den Größen-Frequenzgang in Echtzeit einfach zu zeichnen und zu modifizieren, während das Tool automatisch die exakten Spezifikationen für sie ausfüllt.
Betrachten Sie den Entwurf der folgenden technischen Spezifikation:
Fs:
500Hz
Durchlassband-Frequenz:
0-40Hz
Typ:
Tiefpass
Verfahren:
Elliptisch
Sperrbanddämpfung @ 125Hz:
≥ 80 dB
Passband ripple:
< 0.1dB
Ordnung
Klein wie möglich
Durch die grafische Eingabe der Spezifikationen in den ASN Filter Designer und die Feinabstimmung der Positionen der Entwurfsmarker entwirft das Tool das Filter automatisch als Biquad-Kaskade (diese Terminologie wird in den folgenden Abschnitten erläutert), wählt automatisch die erforderliche Filterordnung und erzeugt im Wesentlichen automatisch die genaue technische Spezifikation des Filters!
Der Frequenzgang eines elliptischen IIR-Tiefpassfilters 5. Ordnung, der die Spezifikationen erfüllt, ist unten dargestellt:
Dieses Tiefpaßfilter 5. Ordnung bildet die Grundlage für die hier geführte Diskussion.
Biquad-IIR-Filter
Die hier besprochene IIR-Filter-Implementierung wird als Biquad bezeichnet, da sie zwei Pole und zwei Nullstellen hat, wie in Abbildung 1 dargestellt. Die Biquad-Implementierung ist besonders nützlich für Festkomma-Implementierungen, da die Auswirkungen der Quantisierung und der numerischen Stabilität minimiert werden. Der Gesamterfolg jeder Biquad-Implementierung hängt jedoch von der verfügbaren Zahlengenauigkeit ab, die ausreichend sein muss, um sicherzustellen, dass die quantisierten Pole immer innerhalb des Einheitskreises liegen.
Abbildung 1: Direkte Form I (Biquad) IIR-Filterrealisierung und Übertragungsfunktion
Bei der Analyse von Abbildung 1 ist zu erkennen, dass die Biquad-Struktur eigentlich aus zwei Rückkopplungspfaden (skaliert mit \(a_1\) und \(a_2\)), drei Vorwärtspfaden (skaliert mit \(b_0, b_1\) und \(b_2\)) und einer Abschnittsverstärkung \(K\) besteht. Somit kann die Filterfunktion von Abbildung 1 durch die folgende einfache rekursive Gleichung zusammengefasst werden:
Bei der Analyse der Gleichung fällt auf, dass die Biquad-Implementierung nur vier Additionen (die nur einen Akkumulator benötigen) und fünf Multiplikationen erfordert, was auf jedem Cortex-M-Mikrocontroller leicht untergebracht werden kann. Die Abschnittsverstärkung K kann auch vor der Implementierung mit den Vorwärtswegkoeffizienten vormultipliziert werden.
Eine Sammlung von Biquad-Filtern wird als Biquad-Kaskade bezeichnet, wie unten dargestellt.
Der ASN Filter Designer kann eine Kaskade von bis zu 50 Biquads entwerfen und implementieren (nur Professional Edition).
Fließkomma-Implementierung
Bei der Implementierung eines Filters in Fließkomma (d. h. unter Verwendung von Arithmetik mit doppelter oder einfacher Genauigkeit) gelten Direct Form II-Strukturen als bessere Wahl als die Direct Form I-Struktur. Die Direct Form II Transposed-Struktur gilt als die numerisch genaueste für die Fließkomma-Implementierung, da die unerwünschten Effekte der numerischen Übersättigung minimiert werden, wie bei der Analyse der Differenzgleichungen zu sehen ist.
Abbildung 2 – Direct Form II Transposed-Struktur, Übertragungsfunktion und Differenzengleichungen
Die Filter Zusammenfassung (siehe Abbildung 3) bietet dem Designer einen detaillierten Überblick über das entworfene Filter, einschließlich einer ausführlichen Zusammenfassung der technischen Spezifikationen und der Filterkoeffizienten, was einen schnellen und einfachen Weg zur Dokumentation Ihres Entwurfs darstellt.
Der ASN Filter Designer unterstützt den Entwurf und die Implementierung sowohl von Single Section als auch von Biquad (Standardeinstellung) IIR-Filtern. Da das CMSIS-DSP-Framework jedoch keine direkte Unterstützung für Single Section IIR-Filter bietet, wird diese Funktion in dieser Application Note nicht behandelt.
Die Implementierung des CMSIS-DSP-Software-Frameworks erfordert die Vorzeicheninversion (d. h. das Umkehren des Vorzeichens) der Rückkopplungskoeffizienten. Um dies zu ermöglichen, kehrt die automatische Code-Generierungs-Engine des Tools das Vorzeichen der Rückkopplungskoeffizienten bei Bedarf automatisch um. In diesem Fall wird der Satz von Differenzgleichungen zu,
Automatische Code-Generierung für Arm-Prozessorkerne über CMSIS-DSP
Die automatische Code-Generierungs-Engine des ASN Filter Designers erleichtert den Export eines entworfenen Filters auf Cortex-M Arm-basierte Prozessoren über das CMSIS-DSP Software-Framework. Die integrierten Analyse- und Hilfefunktionen des Tools unterstützen den Designer bei der erfolgreichen Konfiguration des Designs für den Einsatz.
Alle Entwürfe von Fließkomma-IIR-Filtern müssen auf Single-Precision-Arithmetik und entweder auf einer Direct Form I oder Direct Form II Transposed-Filterstruktur basieren. Wie im vorherigen Abschnitt beschrieben, wird die Direct Form II Transposed-Struktur aufgrund ihrer höheren numerischen Genauigkeit für die Fließkomma-Implementierung befürwortet.
Die Einstellungen für Quantisierung und Filterstruktur finden Sie unter der Registerkarte Q (wie links dargestellt). Durch Einstellen von Arithmetic auf Single Precision und Structure auf Direct Form II Transposed und Klicken auf die Schaltfläche Apply wird die hier betrachtete IIR für das Software-Framework CMSIS-DSP konfiguriert.
Wählen Sie das Arm CMSIS-DSP-Framework aus der Auswahlbox im Filterübersichtsfenster aus:
Der automatisch generierte C-Code auf Basis des CMSIS-DSP-Frameworks für die direkte Implementierung auf einem Arm-basierten Cortex-M-Prozessor ist unten dargestellt:
Wie man sieht, generiert der automatische Code-Generator den gesamten Initialisierungscode, die Skalierung und die Datenstrukturen, die für die Implementierung des IIR über die CMSIS-DSP-Bibliothek benötigt werden. Dieser Code kann direkt in jedem Cortex-M-basierten Entwicklungsprojekt verwendet werden – ein vollständiges Keil-MDK-Beispiel ist auf der Website von Arm/Keil verfügbar. Beachten Sie, dass der Code-Generator des Werkzeugs standardmäßig Code für den Cortex-M4-Kern erzeugt. Bitte entnehmen Sie der folgenden Tabelle die #define-Definition, die für alle unterstützten Kerne erforderlich ist.
ARM_MATH_CM0
Cortex-M0 core.
ARM_MATH_CM4
Cortex-M4 core.
ARM_MATH_CM0PLUS
Cortex-M0+ core.
ARM_MATH_CM7
Cortex-M7 core.
ARM_MATH_CM3
Cortex-M3 core.
ARM_MATH_ARMV8MBL
ARMv8M Baseline target (Cortex-M23 core).
ARM_MATH_ARMV8MML
ARMv8M Mainline target (Cortex-M33 core).
Die automatische Code-Generierung von IIR-Filtern mit komplexen Koeffizienten wird derzeit nicht unterstützt.
Implementieren des Filters im Arm Keil’s MDK
Wie im vorherigen Abschnitt erwähnt, kann der vom Arm CMSIS-DSP Code-Generator erzeugte Code direkt in jedem Cortex-M-basierten Entwicklungsprojekt-Tooling verwendet werden, wie z. B. Arm Keils Industriestandard μVision MDK (Mikrocontroller-Entwicklungskit).
Ein komplettes μVision-Beispiel-IIR-Biquad-Filterprojekt kann von Keils Website heruntergeladen werden und ist, wie unten zu sehen, so einfach wie das Kopieren und Einfügen des Codes und das Vornehmen kleiner Anpassungen am Code.
Das Beispielprojekt nutzt die leistungsstarken Simulationsmöglichkeiten von μVision und ermöglicht die Evaluierung des IIR-Filters auf M0-, M3-, M4- bzw. M7-Cores. Als zusätzlicher Bonus kann auch der Logik-Analysator von μVision verwendet werden, so dass Vergleiche zwischen dem Signal-Analysator des ASN Filter Designers und der Realität auf einem Cortex-M-Kern möglich sind.
Festkomma-Implementierung
Wie bereits erwähnt, ist die direkte Form I-Filterstruktur die beste Wahl für die Festkomma-Implementierung. Vor der Implementierung der Differenzgleichung auf einem Festkommaprozessor müssen jedoch einige wichtige Überlegungen zur Datenskalierung berücksichtigt werden. Da das CMSIS-DSP-Framework nur die Datentypen Q15 und Q31 für IIR-Filter unterstützt, bezieht sich die folgende Diskussion auf eine Implementierung auf einer 16-Bit-Wort-Architektur, d. h. auf Q15.
Quantisierung
Um die Koeffizienten und Ein-/Ausgangszahlen korrekt darzustellen, wird die Systemwortlänge (16 Bit für die Zwecke dieser Application Note) zunächst in ihre Anzahl an Ganzzahlen und Nachkommastellen aufgeteilt. Das allgemeine Format ist gegeben durch:
Q Num of Integers.Fraction length
Wenn wir annehmen, dass alle Datenwerte innerhalb eines Maximal-/Minimalbereichs von \(\pm 1\) liegen, können wir das Format Q0.15 verwenden, um alle Zahlen entsprechend darzustellen. Beachten Sie, dass das Q0.15-Format (oder einfach Q15) ein Maximum von \(\displaystyle 1-2^{-15}=0.9999=0x7FFF\) und ein Minimum von \(-1=0x8000\) (Zweierkomplement-Format) darstellt.
Der ASN Filter Designer kann für die Festkomma-Q15-Arithmetik konfiguriert werden, indem die Spezifikationen für die Wortlänge und die Fraktale Länge in der Registerkarte Q eingestellt werden (siehe Abschnitt Konfiguration für die Details). Ein offensichtliches Problem, das sich bei Biquads zeigt, ist jedoch der Zahlenbereich der Koeffizienten. Da Pole überall innerhalb des Einheitskreises platziert werden können, wird das resultierende Polynom, das für die Implementierung benötigt wird, oft im Bereich \(\pm 2\) liegen, was eine Q14-Arithmetik erfordern würde. Um dieses Problem zu umgehen, werden alle Zähler- und Nennerkoeffizienten über einen biquadischen Post-Scaling-Faktor skaliert, wie unten beschrieben.
Post-Scaling-Faktor
Um sicherzustellen, dass die Koeffizienten in die Spezifikationen für die Wortlänge und die fraktionale Länge passen, enthalten alle IIR-Filter einen Post-Scaling-Faktor, der die Zähler- und Nennerkoeffizienten entsprechend skaliert. Als Folge dieser Skalierung muss der Post-Scaling-Faktor in die Filterstruktur einbezogen werden, um einen korrekten Betrieb zu gewährleisten.
Das Konzept der Post-Scaling wird im Folgenden für eine Biquad-Implementierung der direkten Form I dargestellt.
Abbildung 4: Direkte Form I-Struktur mit Post-Scaling
Durch Vormultiplikation der Zählerkoeffizienten mit der Querschnittsverstärkung \(K\) kann nun jeder Koeffizient mit \(G\) skaliert werden, d. h. \(\displaystyle b_0=\frac{b_0}{G}, b_1=\frac{b_1}{G}, a_1=\frac{a_1}{G}, a_2=\frac{a_2}{G}\) usw. Daraus ergibt sich nun die folgende Differenzengleichung:
Alle im Tool implementierten IIR-Strukturen beinhalten das Konzept des Post-Scaling-Faktors. Diese Skalierung ist für die Implementierung über das Arm CMSIS-DSP-Framework obligatorisch – weitere Details finden Sie im Abschnitt “Konfiguration”.
Verstehen der Filterzusammenfassung
Um die in der ASN Filter Designer Filterzusammenfassung dargestellten Informationen vollständig zu verstehen, zeigt das folgende Beispiel die Filterkoeffizienten, die mit Double Precision Arithmetik und mit Fixed Point Q15 Quantisierung erhalten wurden.
Anwendung der Festkomma-Q15-Arithmetik (beachten Sie die Auswirkungen der Quantisierung auf die Koeffizientenwerte):
Konfigurieren des ASN Filter Designers für Festkomma-Arithmetik
Um ein IIR-Fixed-Point-Filter über das CMSIS-DSP-Framework zu implementieren, müssen alle Designs auf der Fixed-Point-Arithmetik (entweder Q15 oder Q31) und der Direct-Form-I-Filterstruktur basieren.
Die Einstellungen für Quantisierung und Filterstruktur finden Sie unter der Registerkarte Q (wie links dargestellt): Wenn Sie Arithmetic auf Fixed Point und Structure auf Direct Form I einstellen und auf die Schaltfläche Apply klicken, wird die hier betrachtete IIR für das CMSIS-DSP-Software-Framework konfiguriert.
Der Post-Scaling-Faktor ist im CMSIS-DSP-Software-Framework tatsächlich als \( \log_2 G\) implementiert (d. h. eine nach links verschobene Skalierungsoperation, wie in Abbildung 4 dargestellt).
Eingebaute Analytik: Das Tool analysiert automatisch die Filterkoeffizienten der Kaskade und wählt einen geeigneten Skalierungsfaktor. Wie oben zu sehen, ist der größte Minimalwert -1,63143, daher ist ein Post-Scaling-Faktor von 2 erforderlich, um alle Koeffizienten in die Q15-Arithmetik “einzupassen”.
Vergleich von Spektren, die durch unterschiedliche Rechenregeln erhalten wurden
Um die Übersichtlichkeit und die allgemeine Berechnungsgeschwindigkeit zu verbessern, zeigt der ASN Filter Designer nur Spektren (d.h. Magnitude, Phase usw.) an, die auf den aktuellen arithmetischen Regeln basieren. Dies ist etwas anders als bei anderen Werkzeugen, die Multispektren anzeigen, die durch (z. B.) Festkomma– und Doppelpräzisionsarithmetik erhalten wurden. Für alle Benutzer, die Spektren vergleichen möchten, können Sie einfach zwischen den arithmetischen Einstellungen wechseln, indem Sie die Arithmetic methode ändern. Der Designer berechnet dann automatisch die Filterkoeffizienten unter Verwendung der gewählten Rechenregeln und der aktuellen technischen Spezifikation neu. Das Diagramm wird dann unter Verwendung der aktuellen Zoom-Einstellungen aktualisiert.
Automatische Code-Generierung für das Arm CMSIS-DSP-Framework
Wie bei der Fließkomma-Arithmetik wählen Sie das Arm CMSIS-DSP-Framework aus der Auswahlbox im Filter-Übersichtsfenster aus:
Der automatisch generierte C-Code auf Basis des CMSIS-DSP-Frameworks für die direkte Implementierung auf einem Arm-basierten Cortex-M-Prozessor ist unten dargestellt:
Wie beim Fließkommafilter generiert der automatische Code-Generator den gesamten Initialisierungscode, die Skalierung und die Datenstrukturen, die zur Implementierung des IIR über die CMSIS-DSP-Bibliothek benötigt werden. Dieser Code kann direkt in jedem Cortex-M-basierten Entwicklungsprojekt verwendet werden – ein vollständiges Keil-MDK-Beispiel ist auf der Website von Arm/Keil verfügbar. Beachten Sie, dass der Code-Generator des Werkzeugs standardmäßig Code für den Cortex-M4-Kern erzeugt. Bitte entnehmen Sie der folgenden Tabelle die #define -Definition, die für alle unterstützten Kerne erforderlich ist.
ARM_MATH_CM0
Cortex-M0 core.
ARM_MATH_CM4
Cortex-M4 core.
ARM_MATH_CM0PLUS
Cortex-M0+ core.
ARM_MATH_CM7
Cortex-M7 core.
ARM_MATH_CM3
Cortex-M3 core.
ARM_MATH_ARMV8MBL
ARMv8M Baseline target (Cortex-M23 core).
ARM_MATH_ARMV8MML
ARMv8M Mainline target (Cortex-M33 core).
Der Hauptcode der Testschleife (nicht gezeigt) dreht sich um die Funktion arm_biquad_cascade_df2T_f32(), die die Filterung eines Blocks von Eingangsdaten durchführt.
IIR-Filter mit komplexen Koeffizienten werden derzeit nicht unterstützt.
Validierung des Entwurfs mit dem Signal Analyser
Ein Entwurf kann mit dem Signal Analyser validiert werden, wobei sowohl Zeit- als auch Frequenzbereichsdiagramme unterstützt werden. Ein umfassender Signalgenerator ist vollständig in den Signalanalysator integriert, so dass die Entwickler ihre Filter mit einer Vielzahl von Eingangssignalen testen können, wie z. B. Sinuswellen, weißes Rauschen oder sogar externe Testdaten.
Für Festkomma-Implementierungen erlaubt das Tool den Entwicklern, die Overflow-Arithmetikregeln als: Saturate oder Wrap. Außerdem kann die Accumulator Word Length zwischen 16 und 40 Bit eingestellt werden, so dass die Entwickler schnell die optimalen Einstellungen für ihre Anwendung finden können.
Zusätzliche Ressourcen
Digital signal processing: principles, algorithms and applications, J.Proakis and D.Manoloakis
Digital signal processing: a practical approach, E.Ifeachor and B.Jervis.
Digital filters and signal processing, L.Jackson.
Step by step video tutorial of designing an IIR and deploying it to Keil MDK uVision.
Implementing Biquad IIR filters with the ASN Filter Designer and the Arm CMSIS-DSP software framework (ASN-AN025)
https://www.advsolned.com/wp-content/uploads/2020/04/asn25_DFI.png331867ASN consultancy teamhttps://www.advsolned.com/wp-content/uploads/2018/02/ASN_logo.jpgASN consultancy team2021-05-17 14:20:262021-05-17 14:37:02Implementierung von Biquad-IIR-Filtern mit dem ASN Filter Designer und dem Arm CMSIS-DSP Software Framework
Advanced Solutions Nederland is blij te kunnen aankondigen dat het ASN Filter Designer Arm MDK5 software pack nu via Keil beschikbaar is om te downloaden! Het filterpakket biedt MDK-gebruikers een eenvoudige manier om het IP van ASN te gebruiken.
Keil MDK is de meest uitgebreide oplossing voor software-ontwikkeling voor Arm-gebaseerde microcontrollers. Voor MDK worden extra softwarecomponenten en ondersteuning voor microcontroller devices geleverd door softwarepakketten. Download hier
DSP voor ingenieurs: de ASN Filter Designer is de ideale tool om de sensordata snel te analyseren en te filteren. Maak een algoritme binnen enkele uren in plaats van dagen. Wanneer u met sensorgegevens werkt, herkent u deze uitdagingen waarschijnlijk:
Mijn sensordatasignalen zijn te zwak om zelfs maar een analyse te maken. Daarom heb ik versterking van de signalen nodig
Waar ik een vlakke lijn zou verwachten, zien de gegevens eruit als een puinhoop door interferentie en andere vervuiling. Ik moet de gegevens eerst opschonen voordat ik ze analyseer.
Waarschijnlijk heb je tot nu toe dagen of zelfs weken gewerkt aan signaalanalyse en filtering. Het ontwikkelingstraject is over het algemeen langzaam en zeer pijnlijk. Denk maar eens aan het aantal uren dat je had kunnen besparen als je een ontwerptool had gehad die alle algoritmische details voor jou beheerde. ASN Filter Designer is een standaardoplossing voor de industrie die wordt gebruikt door duizenden professionele ontwikkelaars die wereldwijd aan iot-projecten werken.
Onze nauwe samenwerking met Arm en ST zorgt ervoor dat alle ontworpen filters 100% compatibel zijn met alle Arm Cortex-M processoren, zoals de populaire STM32-familie van ST.
Uitdagingen voor ingenieurs
90% van IoT smart sensors zijn gebaseerd op Arm Cortex-M processor technologie
Sensor signal processing is moeilijk
Sensoren hebben moeite met interferentie en allerlei ongewenste componenten
Hoe ontwerp ik een filter dat voldoet aan mijn requirements?
Hoe kan ik mijn ontworpen filter controleren op testdata?
Voor betere product performance is schone sensor data nodig
Tijdrovend proces om een filter op een embedded processor te implementeren
Tijd is geld!
Ontwerpers verzanden vaak met traditionele tooling. Deze vereist meestal een iteratieve, trial and error aanpak of deskundige kennis. Met deze aanpak gaat kostbare tijd verloren. ASN Filter Designer helpt u met een interactieve ontwerpmethode. Hierbij voert de tool automatisch de technische specificaties in op basis van eisen die de gebruiker grafisch heeft ingevoerd.
Snelle ontwikkeling van het DSP-algoritme
Volledig gevalideerd filterontwerp: geschikt voor toepassing in DSP, Arm microcontroller, FPGA, ASIC of PC-toepassing
Automatische gedetailleerde ontwerpdocumentatie: de Filter Designer helpt je met documenatie, waardoor je de peer review kunt versnellen en projectrisico’s verlaagt
Eenvoudige overdracht: projectdossier, documentatie en testresultaten bieden een gemakkelijk manier voor overdracht aan collega’s of andere teams
Gemakkelijk in te passen in nieuwe scenario’s: het ontwerp kan eenvoudig worden aangepast aan andere eisen en scenario’s, zoals 60Hz interferentieonderdrukking op de voedingslijn, in plaats van de Europese 50Hz.
ASN Filter Designer: de snelle en intuitieve filter designer
De ASN Filter Designer is het ideale hulpmiddel om sensorgegevens snel te analyseren en filteren. Indien nodig kun je jouw gegevens eenvoudig naar tools als Matlab en Python exporteren voor verdere analyse. Daarom is het ideaal voor ingenieurs die een krachtige tool voor signaalanalyse nodig hebben en een datafilter voor hun IOT-toepassing moeten maken. Zeker als je af en toe een datafilter moet maken. Vergeleken met andere tools creeer je een algoritme binnen enkele uren in plaats van dagen.
Exporteer jouw algoritmes naar Matlab, Python of een Arm microcontroller
Je kunt veel tijd besparen doordat je met ASN Filter Designer algoritmes eenvoudig kunt implementeren in Matlab, Python of direct op een Arm-microcontroller omdat de Filter Designer automatisch code generateert.
Onmiddelijke verlichting
Denk eens aan het aantal uren dat je had kunnen besparen als je een ontwerptool had gehad die alle algoritmische details voor je beheerde.
ASN Filter Designer is een standaardoplossing in de sector die wordt gebruikt door duizenden professionele ontwikkelaars die wereldwijd aan ivd-projecten werken. Onze nauwe samenwerking met Arm en ST zorgt ervoor dat alle filters 100% compatibel zijn met alle Arm Cortex-M processoren.
Hoeveel pijnverzachting kun je voor 145 Euro kopen?
Omdat veel technici onze ASN Filterontwerper voor korte tijd nodig hebben, is een licentie van 145 euro voor slechts 3 maanden mogelijk!
Vraag jezelf maar af: is 145 Euro een eerlijke prijs om te betalen voor onmiddellijke pijnverlichting en resultaat? Wij denken van wel. Bovendien hebben we een licentie voor 1 jaar en zelfs een eeuwigdurende licentie. Download de demo om het zelf te zien of neem contact met ons op voor meer informatie
https://www.advsolned.com/wp-content/uploads/2019/11/Worker-pipelines.jpg9981500ASN consultancy teamhttps://www.advsolned.com/wp-content/uploads/2018/02/ASN_logo.jpgASN consultancy team2020-07-27 13:06:402020-08-25 16:42:46How DSP for oil, gas and flow measurement can benefit from the ASN Filter Designer
Finite impulse response (FIR) filters are useful for a variety of sensor signal processing applications, including audio and biomedical signal processing. Although several practical implementations for the FIR exist, the Direct Form Transposed structure offers the best numerical accuracy for floating point implementation. However, when considering fixed point implementation on a micro-controller, the Direct Form structure is considered to be the best choice by virtue of its large accumulator that accommodates any intermediate overflows.
This application note specifically addresses FIR filter design and implementation on a Cortex-M based microcontroller with the ASN Filter Designer for both floating point and fixed point applications via the Arm CMSIS-DSP software framework. Details are also given (including an Arm reference software pack) regarding implementation of the FIR filter in Arm/Keil’s MDK industry standard Cortex-M micro-controller development kit.
Introduction
ASN Filter Designer provides engineers with a powerful DSP experimentation platform, allowing for the design, experimentation and deployment of complex FIR digital filter designs for a variety of sensor measurement applications. The tool’s advanced functionality, includes a graphical based real-time filter designer, multiple filter blocks, various mathematical I/O blocks, live symbolic math scripting and real-time signal analysis (via a built-in signal analyser). These advantages coupled with automatic documentation and code generation functionality allow engineers to design and validate a digital filter within minutes rather than hours.
The Arm CMSIS-DSP (Cortex Microcontroller Software Interface Standard) software framework is a rich collection of over sixty DSP functions (including various mathematical functions, such as sine and cosine; IIR/FIR filtering functions, complex math functions, and data types) developed by Arm that have been optimised for their range of Cortex-M processor cores.
The framework makes extensive use of highly optimised SIMD (single instruction, multiple data) instructions, that perform multiple identical operations in a single cycle instruction. The SIMD instructions (if supported by the core) coupled together with other optimisations allow engineers to produce highly optimised signal processing applications for Cortex-M based micro-controllers quickly and simply.
ASN Filter Designer fully supports the CMSIS-DSP software framework, by automatically producing optimised C code based on the framework’s DSP functions via its code generation engine.
Designing FIR filters with the ASN Filter Designer
ASN Filter Designer provides engineers with an easy to use, intuitive graphical design development platform for FIR digital filter design. The tool’s real-time design paradigm makes use of graphical design markers, allowing designers to simply draw and modify their magnitude frequency response requirements in real-time while allowing the tool automatically fill in the exact specifications for them.
Consider the design of the following technical specification:
Fs:
500Hz
Passband frequency:
0-25Hz
Type:
Lowpass
Method:
Parks-McClellan
Stopband attenuation @ 125Hz:
≥ 80 dB
Passband ripple:
< 0.01dB
Order:
Small as possible
Graphically entering the specifications into the ASN Filter Designer, and fine tuning the design marker positions, the tool automatically designs the filter), automatically choosing the required filter order, and in essence – automatically producing the filter’s exact technical specification!
The frequency response of a filter meeting the specification is shown below:
This Lowpass filter will form the basis of the discussion presented herein.
Parks–McClellan algorithm
The Parks–McClellan algorithm is an iterative algorithm for finding the optimal Chebyshev FIR filter. The algorithm uses an indirect method for finding the optimal filter coefficients, that offers a degree of flexibility over other FIR design methods, in that each band may be individually customised in order to suit the designer’s requirements.
The primary FIR filter designer UI implements the Parks-McClellan algorithm, allowing for the design of the following filter types:
Filter Types
Description
Lowpass
Designs a lowpass filter.
Highpass
Designs a highpass filter.
Bandpass
Designs a bandpass filter.
Bandstop
Designs a bandstop filter.
Multiband
Designs a multiband filter with an arbitrary frequency response.
Hilbert transformer
Designs an all-pass filter with a -90 degree phase shift.
Differentiator
Designs a filter with +20dB/decade slope and +90 degree phase shift.
Double Differentiator
Designs a filter with +40dB/decade slope and a +90 degree phase shift.
Integrator
Designs a filter with -20dB/decade slope and a -90 degree phase shift.
Double Integrator
Designs a filter with -40dB/decade slope and a -90 degree phase shift.
These ten filter types provide designers with a great deal of flexibility for a variety of IoT applications. Design requirements may be simply specified via the use of the design markers. In all cases, the tool will automatically calculate the required filter order to meet the designer’s specification.
The Parks-McClellan algorithm is an optimal Chebyshev FIR design method. However, the algorithm may not converge for some specifications. In such cases, increasing the distance between the design marker bands generally helps.
Other FIR design methods
Designers looking to experiment with other types of FIR design methods may use the ASN FilterScript live symbolic math scripting language. The scripting language supports over 65 scientific commands and provides designers with a familiar and powerful programming language, while at the same time allowing them to implement complex symbolic mathematical expressions. The following functions are supported:
Function
Description
movaver
Moving average FIR filter design.
firwin
FIR filter design based on the Window method.
firarb
Designs an FIR Window based filter with an arbitrary magnitude response.
firkaiser
Designs an FIR filter based on the Kaiser window method.
firgauss
Designs an FIR Gaussian lowpass filter.
savgolay
Design an FIR Savitzky-Golay lowpass smoothing filter.
Please refer to the ASN FilterScript reference guide for more details.
All filters designed in ASN FilterScript are designed using double precision arithmetic in the H2 filter sandbox. An H2 filter must be transformed to an H1 (primary) filter for deployment.
This may be simply achieved via the P-Z options menu:
The re-optimise method automatically analyses and converts the H2 filter into an H1 filter.
Floating point implementation
When implementing a filter in floating point (i.e. using double or single precision arithmetic) the Direct Form Transposed structure is considered the most numerically accurate. This can be readily seen by analysing the difference equations below (used for implementation), as the undesirable effects of numerical swamping are minimised, since floating point addition is performed on numbers of similar magnitude.
The quantisation and filter structure settings used to implement the FIR can be found under the Q tab (as shown below).
Despite the Direct FormTransposed structure being the most efficient for floating point implementation, the Arm CMSIS-DSP library does not currently support the Direct FormTransposed structure for FIR filters. Only the Direct Form structure is supported.
Setting Arithmetic to Single Precision and Structure to Direct Form and clicking on the Apply button configures the FIR considered herein for the CMSIS-DSP software framework.
The optimised functions within the Arm CMSIS-DSP framework currently support Single Precision arithmetic only.
Support for Double Precision and the Direct FormTransposed structure will be added in future releases.
Fixed point implementation
When implementing a filter with fixed point arithmetic, the Direct Form structure is considered to be the best choice by virtue of its large accumulator that accommodates any intermediate overflows. The Direct Form structure and associated difference equation are shown below.
Direct form structure (for fixed point implementation)
The CMSIS-DSP Framework supports Q7, Q15 and Q31 coefficient quantisation only. The options may be simply specified via the quantisation tab Q as shown below:
The tool’s inbuilt analytics (shown in the textbox) are intended to help the designer choose the most suitable quantisation settings.
As seen on the left, the tool has recommended a RFWL (recommended fraction length) of 15bits (Q15) for the coefficients, which is as required.
The Direct form structure is chosen over the Direct Form Transposed as a single (40-bit) accumulator can be used. The tool’s automatic code generator makes use of CMSIS-DSP’s 64-bit accumulators functions, so that the final C code deployed to a Cortex-M device will not overflow.
Deploying Arm CMSIS-DSP compliant code
The ASN Filter Designer’s automatic code generation engine facilitates the export of a designed filter to Cortex-M Arm based processors via the Arm CMSIS-DSP software framework. The tool’s built-in analytics and help functions assist the designer in successfully configuring the design for deployment.
Select the Arm CMSIS-DSP framework from the selection box in the filter summary window:
The automatically generated C code based on the Arm CMSIS-DSP framework for direct implementation on an Arm based Cortex-M processor is shown below:
This code may be directly used in any Cortex-M based development project.
Arm Keil’s MDK (uVision)
As mentioned above, the code generated by the Arm CMSIS DSP code generator may be directly used in any Cortex-M based development project tooling, such as Arm Keil’s industry standard uVision MDK (micro-controller development kit).
The following Arm software pack is available on Keil’s website for using this code directly with Keil uVision MDK.
https://www.advsolned.com/wp-content/uploads/2020/04/df2T_fir.png306900ASN consultancy teamhttps://www.advsolned.com/wp-content/uploads/2018/02/ASN_logo.jpgASN consultancy team2020-06-11 17:36:292022-11-25 14:51:35Implementing FIR filters with the ASN Filter Designer and the Arm CMSIS-DSP software framework
Advanced Solutions Nederland is happy to announce that the ASNFD filtering Arm MDK5 software pack now avalailable for download! The filtering pack provides MDK users with an easy way of ASN’s IP.
Keil MDK is the most comprehensive software development solution for Arm-based microcontrollers. For MDK, additional software components and support for microcontroller devices is provided by software packs. Download here
https://www.advsolned.com/wp-content/uploads/2020/03/ARM-Keil.png204882ASN consultancy teamhttps://www.advsolned.com/wp-content/uploads/2018/02/ASN_logo.jpgASN consultancy team2020-03-07 14:53:332022-12-13 16:00:12ASN Filter Designer IP blocks now available via ARM-Keil!
Modern embedded processors, software frameworks and design tooling now allow engineers to apply advanced measurement concepts to smart factories as part of the I4.0 revolution.
In recent years, PM (predictive maintenance) of machines has received great attention, as factories look to maximise their production efficiency while at the same time retaining the invaluable skills of experienced foremen and production workers.
Traditionally, a foreman would walk around the shop floor and listen to the sounds a machine would make to get an idea of impending failure. With the advent of I4.0 AIoT technology, microphones, edge DSP algorithms and ML may now be employed in order to ‘listen’ to the sounds a machine makes and then make a classification and prediction.
One of the major challenges is how to make a computer hear like a human. In this article we will discuss how sound weighting curves can make a computer hear like a human, and how they can be deployed to an Arm Cortex-M microcontroller for use in an AIoT application.
Physics of the human ear
An illustration of the human ear shown below. As seen, the basic task of the ear is to translate sound (air vibration) into electrical nerve impulses for the brain to interpret.
The ear achieves this via three bones (Stapes, Incus and Malleus) that act as a mechanical amplifier for vibrations received at the eardrum. These amplified sounds are then passed onto the Cochlea via the Oval window (not shown).
The Cochlea (shown in purple) is filled with a fluid that moves in response to the vibrations from the oval window. As the fluid moves, thousands of nerve endings are set into motion. These nerve endings transform sound vibrations into electrical impulses that travel along the auditory nerve fibres to the brain for analysis.
Modelling perceived sound
Due to complexity of the fluidic mechanical construction of the human auditory system, low and high frequencies are typically not discernible. Researchers over the years have found that humans are most perceptive to sounds in the 1-6kHz range, although this range varies according to the subject’s physical health.
This research led to the definition of a set of weighting curves: the so-called A, B, C and D weighting curves, which equalises a microphone’s frequency response. These weighting curves aim to bring the digital and physical worlds closer together by allowing a computerised microphone-based system to hear like a human.
The A-weighing curve is the most widely used as it is mandated by IEC-61672 to be fitted to all sound level meters. The B and D curves are hardly ever used, but C-weighting may be used for testing the impact of noise in telecoms systems.
The frequency response of the A-weighting curve is shown above, where it can be seen that sounds entering our ears are de-emphasised below 500Hz and are most perceptible between 0.5-6kHz. Notice that the curve is unspecified above 20kHz, as this exceeds the human hearing range.
ASN FilterScript
ASN’s FilterScript symbolic math scripting language offers designers the ability to take an analog filter transfer function and transform it to its digital equivalent with just a few lines of code.
The analog transfer functions of the A and C-weighting curves are given below:
\(H_A(s) \approx \displaystyle{7.39705×10^9 \cdot s^4 \over (s + 129.4)^2\quad(s + 676.7)\quad (s + 4636)\quad (s + 76655)^2}\)
\(H_C(s) \approx \displaystyle{5.91797×10^9 \cdot s^2\over(s + 129.4)^2\quad (s + 76655)^2}\)
These analog transfer functions may be transformed into their digital equivalents via the bilinear() function. However, notice that \(H_A(s) \) requires a significant amount of algebracic manipulation in order to extract the denominator cofficients in powers of \(s\).
Convolution
A simple trick to perform polynomial multiplication is to use linear convolution, which is the same algebraic operation as multiplying two polynomials together. This may be easily performed via FilterScript’s conv() function, as follows:
y=conv(a,b);
As a simple example, the multiplication of \((s^2+2s+10)\) with \((s+5)\), would be defined as the following three lines of FilterScript code:
a={1,2,10};
b={1,5};
y=conv(a,b);
which yields, 1 7 20 50 or \((s^3+7s^2+20s+50)\)
For the A-weighting curve Laplace transfer function, the complete FilterScript code is given below:
ClearH1; // clear primary filter from cascade
Main() // main loop
a={1, 129.4};
b={1, 676.7};
c={1, 4636};
d={1, 76655};
aa=conv(a,a); // polynomial multiplication
dd=conv(d,d);
aab=conv(aa,b);
aabc=conv(aab,c);
Na=conv(aabc,dd);
Nb = {0 ,0 , 1 ,0 ,0 , 0, 0}; // define numerator coefficients
G = 7.397e+09; // define gain
Ha = analogtf(Nb, Na, G, "symbolic");
Hd = bilinear(Ha,0, "symbolic");
Num = getnum(Hd);
Den = getden(Hd);
Gain = getgain(Hd)/computegain(Hd,1e3); // set gain to 0dB@1kHz
Frequency response of analog vs digital A-weighting filter for \(f_s=48kHz\). As seen, the digital equivalent magnitude response matches the ideal analog magnitude response very closely until \(6kHz\).
The ITU-R 486–4 weighting curve
Another weighting curve of interest is the ITU-R 486–4 weighting curve, developed by the BBC. Unlike the A-weighting filter, the ITU-R 468–4 curve describes subjective loudness for broadband stimuli. The main disadvantage of the A-weighting curve is that it underestimates the loudness judgement of real-world stimuli particularly in the frequency band from about 1–9 kHz.
Due to the precise definition of the 486–4 weighting curve, there is no analog transfer function available. Instead the standard provides a table of amplitudes and frequencies – see here. This specification may be directly entered into FilterScript’s firarb() function for designing a suitable FIR filter, as shown below:
Frequency response of an ITU-R 468-4 FIR filter designed with FilterScript’s firarb() function for \(f_s=48kHz\)
As seen, FilterScript provides the designer with a very powerful symbolic scripting language for designing weighting curve filters. The following discussion now focuses on deployment of the A-weighting filter to an Arm based processor via the tool’s automatic code generator. The concepts and steps demonstrated below are equally valid for FIR filters.
Automatic code generation to Arm processor cores via CMSIS-DSP
The ASN Filter Designer’s automatic code generation engine facilitates the export of a designed filter to Cortex-M Arm based processors via the CMSIS-DSP software framework.
The tool’s built-in analytics and help functions assist the designer in successfully configuring the design for deployment. Professional licence users may expedite the deployment by using the Arm deployment wizard that automates the steps described below.
Before generating the code, the H2 filter (i.e. the filter designed in FilterScript) needs to be firstly re-optimised (transformed) to an H1 filter (main filter) structure for deployment. The options menu can be found under the P-Z tab in the main UI.
All floating point IIR filters designs must be based on Single Precision arithmetic and either a Direct Form I or Direct Form II Transposed filter structure. The Direct Form II Transposed structure is advocated for floating point implementation by virtue of its higher numerically accuracy.
Quantisation and filter structure settings can be found under the Q tab (as shown on the left). Setting Arithmetic to Single Precision and Structure to Direct Form II Transposed and clicking on the Apply button configures the IIR considered herein for the CMSIS-DSP software framework.
Select the Arm CMSIS-DSP framework from the selection box in the filter summary window:
The automatically generated C code based on the CMSIS-DSP framework for direct implementation on an Arm based Cortex-M processor is shown below:
As seen, the ASN Filter Designer’s automatic code generator generates all initialisation code, scaling and data structures needed to implement the A-weighting filter IIR filter via Arm’s CMSIS-DSP library. A detailed help tutorial is available by clicking on the Show me button.
Sanjeev is an AIoT visionary and expert in signals and systems with a track record of successfully developing over 25 commercial products. He is a Distinguished Arm Ambassador and advises top international blue chip companies on their AIoT solutions and strategies for I4.0, telemedicine, smart healthcare, smart grids and smart buildings.
https://www.advsolned.com/wp-content/uploads/2019/10/aweightingcurve.png420560Dr. Sanjeev Sarpalhttps://www.advsolned.com/wp-content/uploads/2018/02/ASN_logo.jpgDr. Sanjeev Sarpal2019-10-03 21:22:482023-08-04 10:49:04A-weighting equalisation: Designing and deploying to Arm Cortex-M microcontrollers
